A Novel Approach for Leakage Power Reduction Techniques in 65nm Technologies

摘要

The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk thereby evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality isenabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all overthe world today, the battery-powered electronic system forms the backbone. To maximize the battery life,the tremendous computational capacity of portable devices such as notebook computers, personalcommunication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers hasto be realized with very low power requirements. Leakage power consumption is one of the major technicalproblem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage powerminimization techniques have been presented in this paper a novel Leakage reduction technique isdeveloped in Cadence virtuoso in 65nm regim with the combination of stack with sleepy keeper approachwith Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%,Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24%with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.