Thermal Resistance Reduction in Power MOSFETs Integrated in a 65nm SOI Technology

摘要

The static and dynamic analysis of the thermal resistance (R_(TH)) in 65nm SOI DriftMOS power devices is presented in this work. Experiment and numerical simulation are both used to compare DriftMOS devices integrated in 65nm and 130nm SOI technologies. Important R_(TH) drop (between 40% and 60%) is found by experiment at 65nm technology, basically due to the thinner buried oxide (BOX) layer. However, numerical simulation reveals a lower R_(TH) reduction in the hottest point of the SOI active layer, shifted down about 15%. Furthermore, the R_(TH) dependence with device geometrical parameters is investigated and the different layer contributions to the global thermal resistance are identified.