Design Space Exploration for the Design of Reliable SRAM-based FPGA Systems

摘要

This paper presents a design space exploration approach for the design of SRAM -based FPGAs with Single Event Upsets fault mitigation capabilities, exploiting the feature of partial, dynamic reconfiguration ordered by the target platform. In fact, in this scenario, several techniques are available and they can be applied at different granularity levels; thus, we propose a support for exploring the different alternatives by means of a framework taking into account several figures of merit, based on genetic algorithms. The several elements taken into account for evaluating the different solutions are here analyzed and discussed, and the application of the methodology and framework to some case studies is reported, allowing both a tuning of the metrics and the analysis of the identified most interesting solutions, which do not correspond, in general, to the trivial ones.