THRESHOLD VOLTAGE CONTROL IN POLYSILICON OR FULLY SILICIDED-Hf-BASED GATE DIELECTRIC PMOSFETS USING CONTROLLED LATERAL OXIDATION

摘要

Large threshold-voltage (V_t) shifts are seen in PMOSFETs with Hf-based highK gate dielectric and polysilicon gates. The polysilicon-highK interface can be modified by introducing a thin interfacial oxide layer using a controlled lateral oxidation (CLO) step after gate patterning. This can reduce the threshold voltage shift to within 0.1 V of SiO_2 reference for devices with gate length <1μm. The benefit of lower Vt with the lateral oxidation comes at the expense of increased EOT. We therefore tried CLO using fullysilicided NiSi gates since the poly-depletion gain can offset the EOT increase. Our results show that the V_t difference between SiO_2 and HfSiO is within 50mV. Moreover, the Ion-Ioff performance shows that while poly gates are lower in performance due to high Vt, the FUSI gates give lon/Ioff at 1.1V of 180 (pA/gm)/20 (pA/μm) for both Hf-silicates and conventional Si02. Interfacial modification using CLO can be a potential integration solution for highK gate dielectrics with polysilicon gates.