In pass-transistor logic circuits, an AND gate is implemented by two MOSFETs in series. We believe that it can be replaced by a single double-gate SOI MOSFET, in this way we can reduce the gate delay, and also shrink the area at the same time. Furthermore, this implementation is not limited to the pass-transistor AND gate, it applies to any CMOS logic circuits with stacking transistor structures, such as NAND, NOR and XOR.
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