A three-order model-being as simple as the commonly used T model-is presented for deep-submicron VLSI interconnects. Yet we show that this mdoel yields less than 1percent error from exact distributed RC ladder network modeling for the roadmap technologies down to 0.18mum and up to 5 GHZ operating frequency. Being accurate, simple, and analytic, i.e., expressed directly in terms of the length and width of an interconnect wire, this model can be used for physical design optimization. Its accuracy and efficiency are demonstrated from numerical comparison with existing models, by using RCWIRE, a prototype SPICE-in, SPICE-out, model generator of interconnects.
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