A Design Space Comparison of 6T and 8T SRAM Core-Cells

摘要

We present a comparison of 6T and 8T SRAM design spaces for low-power 65nm and 45nm CMOS technologies based on simulations using a multi-objective optimization framework. The influence of a bit-line column multiplexer (MUX) on the 8T design space is shown. We demonstrate that 6T and 8T cells show differing area scaling behavior across the whole design space. We identify points on the area-performance trade-off curves that bound regions where either 6T or 8T SRAM cells are optimal.