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Requirements and restrictions in optimizing homogeneous and planar doped barrier vertical MOSFETs

机译:优化均匀平面掺杂屏障垂直MOSFET的要求和限制

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Systematic simulations of ultra-short channel vertical MOSFETs and planar doped barrier MOSFETs (PDBFET) have been carried out in order to understand how to best fulfill the following requirements: high doping in order to prevent punch through, low mobility reduction due to doping, sufficiently low field in order to prevent impact ionization, a small threshold voltage and a near ideal subthreshold swing for the desired low supply voltage, and a low channel conductance. We find that the technologically more elaborate PDBFET matches these diverse requirements much better, since the i-regions forming most of the channel reduce the lateral field near source and drain, whereas the highly doped barrier prevents punch through and provides the required threshold voltage. At the same time, the scattering in the i-regions is reduced, resulting in only a low mobility reduction.
机译:已经进行了系统模拟超短通道垂直MOSFET和平面掺杂屏障MOSFET(PDBFET),以便了解如何最好地满足以下要求:高掺杂,以防止冲压,由于掺杂引起的低移动性降低,充分低场,以防止冲击电离,小阈值电压和近乎理想的亚阈值摆动,用于所需的低电源电压,以及低通道电导。我们发现,技术上更精细PDBFET匹配这些不同的要求好得多,因为形成的大部分信道的i区域减少横向场邻近源极和漏极,而高度掺杂的阻挡件防止穿通,并提供所需的阈值电压。同时,减少了I-e区中的散射,导致仅降低迁移率降低。

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