Characterization and model of the hot-carrier-induced offsetvoltage of analog CMOS differential stages

摘要

Using a specifically developed measurement setup and a teststructure typical for analog applications, high precision measurementsof the stress-induced offset voltage degradation of differential pairsare realized. A model is developed that traces back thehot-carrier-induced offset voltage to a single transistor parameter thussimplifying greatly statements about analog circuit reliability.Extrapolation to operating conditions yields valuable information foranalog design in the sub-μm CMOS regime