Using a specifically developed measurement setup and a test structure typical for analog applications, high precision measurements of the stress-induced offset voltage degradation of differential pairs are realized. A model is developed that traces back the hot-carrier-induced offset voltage to a single transistor parameter thus simplifying greatly statements about analog circuit reliability. Extrapolation to operating conditions yields valuable information for analog design in the sub-/spl mu/m CMOS regime.
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机译:使用专门开发的测量设置和典型的模拟应用测试结构,可以实现对差分对的应力引起的偏置电压降级的高精度测量。开发了一个模型,该模型可将热载流子引起的偏移电压追溯到单个晶体管参数,从而大大简化了有关模拟电路可靠性的陈述。外推到工作条件可为sub / splμ/ m CMOS制程中的模拟设计提供有价值的信息。
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