Floating-body problems and benefits in fully depleted SOI CMOS VLSIcircuits

摘要

A physical model for the fully depleted submicron SOI(silicon-on-insulator) MOSFET is described and used to assess problemsand possible benefits in SOI CMOS VLSI digital circuits that result fromthe parasitic bipolar junction transistor (BJT) in the floating-bodydevice. It is shown that the problems overwhelm the benefits, and hencemust be alleviated by controlling the activation of the BJT via devicedesign tradeoffs. A feasible approach to the needed design optimizationis demonstrated by device/circuit simulations. The physical model forthe fully depleted SOI MOSFET described here has been written intoSPICE2 source code