Systematic approach to correct critical patterns induced by the lithography process at the full-chip level

摘要

Abstract: This paper present a systematic approach to correctcritical patterns, which are more prone to defects dueto the photo lithography process, at the full-chiplevel for sub-quarter micron CMOS applications. In thefirst stage of the photo lithography process forintegrated circuits (IC), the bridging failure betweenpatterns in a photoresist layer has been foundoccasionally. The small process margin in patterningplays a key part of the device yield drop, when processconditions or production lines are changed. However, itis a very difficult and time-consuming job to find andcorrect all the possible critical patterns which mightcause failure. Test patterns with variousline-and-spaces are designed and simulated using theaerial image model and the third order polynomialfunction of critical patterns. The DRC software withthe rules searches an entire area of the IC layout. Theproposed approach to extract critical patterns is costeffective and fast compared to the evaluation of alayout using a photo lithography simulator at thefull-chip level. Applying this methodology to 256M DRAMwith 0.25 $mu@m minimum design width in the peripheryand core area, all bridge defects found beforecorrection can be removed. Furthermore, it will be auseful tool to the product engineer who should indicatemonitoring patterns, which are sensitive to thelithography process margin. !7