Approach to full-chip simulation and correction of stencil mask distortion for proximity electron lithography

摘要

An approach for simulating the in-plane displacements of mask patterns induced by pattern-density gradients over thin membranes of a stencil mask as used for proximity electron lithography (PEL) has been proposed and demonstrated for the contact layer of a real device in the 65 nm node. The comparison of simulation and experiment shows that full-chip analysis is feasible if the method for tuning the boundary condition for the simulation to match with the experiment is established.