A wafer level package (WLP) has been developed as a cost effectivepackaging method compared to the μBGA package, and especially appliedto the Rambus DRAM (RDRAM) package. The maximum allowable thickness ofthe stress buffer layer on the WLP is limited to about 20 μm, due tothe limitation of the present spin coating process technology. Hence,the thickness of the stress buffer layer is much smaller than that ofthe elastomer (175 pm) used as a dielectric layer in the μBGApackage. Consequently, due to this extremely small distance between themetal traces on the WLP and the silicon substrate, the capacitiveloading of the WLP on the RIMM (Rambus in-line memory module) issignificantly increased. The increased capacitive loading by the WLPresults in a decrease in the effective line impedance and an increase inthe propagation delay on the RIMM, while the target line impedance onthe RIMM is 28 Ω±10%. Therefore, careful designconsiderations are required at the package design level and at themodule design level, to compensate for the increased capacitive loadingby the WLP. In this paper, we firstly introduce the equivalent circuitmodel of the WLP interconnection lines using the S-parameter measurementin the microwave frequency region up to 5 GHz. Then, we suggest theelectrical design methodology of the WLP and the module to compensatefor the increased loading capacitance of the WLP
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