Virtually Nonvolatile Retention SRAM cell Using Dual-Mode Inverters

摘要

We propose a virtually nonvolatile retention SRAM (VNR-SRAM) cell that has a potential as a basis for hierarchical memories such as caches and register files in highly energy-efficient power-gating logic systems. The proposed VNR-SRAM cell can retain its data using an ultralow supply-voltage or a shutdown-state voltage induced by power-switches. The cell is configured with dual-mode inverters that act as a Schmitt trigger inverter for ultralow-voltage retention and as a conventional or boosted inverter for ordinary-voltage normal operations. Design methodologies and energy performance of the VNR-SRAM cell are investigated.