Nonvolatile SRAM memory cell and nonvolatile semiconductor memory device

摘要

A nonvolatile SRAM memory cell and a nonvolatile semiconductor memory device capable of reducing a capacitance component added to an SRAM portion are provided. An N well NW is disposed in the center of a memory cell region, and P wells PWa and PWb are disposed on both sides of the memory cell region so as to sandwich the N well NW. First and second load transistors 21a and 21b are formed in the N well NW. The first access transistor 17, the first drive transistor 22a, and the first nonvolatile memory element 28a are formed in the P well PWa, and the second access transistor 18, the second drive transistor 22b, and the second nonvolatile memory element 28b are formed in the P well PWb. The first nonvolatile memory element 28a is disposed on one of the both sides of the SRAM portion, and the second nonvolatile memory element 28b is disposed on the other side. [Selection] Figure 3