ULK optimization for Cu/ULK(K=2.5) BEOL interconnect TDDB and EM improvement at 28/14nm technology node and beyond

摘要

As CMOS is being scaled down to 28nm node and beyond, it is necessary to reduce k value in order to improve RC delay. ULK (ultra-low k) (k<;2.55) has been implemented into production from 45/40nm node. Compared with low-K film, ultra-low K film is more porous, softer and hydrophilic intrinsically. It is easy to be damaged by plasma, stress, thermal or aqueous environments. It brings more challenges for reliability improvement. This paper focuses mainly on ULK process optimization through simple key parameter optimization to improve voltage break down (VBD) and time-dependent dielectric breakdown (TDDB) and electro migration (EM) performance without scarifying RC delay.