Optimization of backside metal deposition in power IC process for suppression of wafer warpage and film peeling issue

摘要

In power IC manufacture process, wafer backside metal deposition as contact layer is a critical step to improve whole chip contact resistance and thermal conduction. The conventional metal films applied in backside deposition are titanium (Ti), Nickel (Ni) and Silver (Ag) with physical vapor deposition (PVD) technique. In order to reduce contact resistance, higher metal film thickness is requested. This result in high wafer stress and warpage challenge. The adhesion between wafer backside silicon and Ti/Ni/Ag film is also critical index to ensure electrics stability. In general, wafer substrate roughness, metal process temperature and out-gassing control are key points in process optimization. In this paper, we will introduce basic process of backside metal deposition and discuss the experiments / results on wafer warpage and film peeling suppression.