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Charge-trap flash memory devices fabricated with nano-scale patterns on the Si3N4 trapping layer

机译:充电 - 陷阱闪存器件,在Si3N4捕获层上制造了纳米尺度模式

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We proposed a novel CTF memory structure with surface patterned Si3N4 trap layers, in order to enhance the memory window and the performance for ultra-high density CTF devices. Due to the enlargement of surface memory-trap densities, the CTF devices with nano-scale surface patterns on the Si3N4 trap layer by NSL showed increased memory windows and improved program properties. In addition, the reasonable reliability, including data retention of 10 years and endurance of 104 P/E cycles, was obtained.
机译:我们提出了一种具有表面图案化Si3N4陷阱层的新型CTF存储器结构,以增强存储器窗口和超高密度CTF器件的性能。由于表面存储器陷阱密度的放大,通过NSL的Si3N4陷阱层上具有纳米级表面图案的CTF器件显示出增加的存储器窗口和改进的程序性质。此外,获得合理的可靠性,包括10年的数据保留和10次 4 p / E循环的耐久性。

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