A 1.6GHz 16×16-bit low-latency pipelined booth multiplier

摘要

This paper presents a high-speed 16×16-bit CMOS pipelined booth multiplier. By using new partial product generation and booth encoder circuits and a novel adder, speed of pipelined multipliers is improved. By these new architectures, final adder performs 25 bit addition in only two cycles with high speed (1.6 GHz). Due to lower number of cycles (5 clock cycles), delay of the overall circuit is only 3.1ns and besides power consumption is decreased so that at a data rate of 1 GHz and under the supply voltage of 3.3V, power consumption is 176mW. This multiplier is implemented in TSMC 0.35μm CMOS technology.