首页> 外文会议>2011 IEEE Computer Society Annual Symposium on VLSI >Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET
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Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET

机译:Gate-S / D重叠,非对称和独立栅极特性对纳米DGMOSFET的短沟道效应最小化的影响

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摘要

Asymmetric and independent gate features of DGMOSFETs are explored recently for nano scale applications. This paper investigates minimization of short channel effects based on the independent gate, gate-S/D under lap and asymmetric (in front and back gate oxide thickness, gate work functions and gate bias) features of DGMOSFETs. Novel analytical models for threshold voltage, threshold voltage roll-off and DIBL effects of an under lap DGMOSFET with asymmetric, independent gate features are proposed and validated with numerical simulation results. Overall, results show that gate under lap feature and asymmetry brought in DGMOSFET by proper tuning of back gate bias, back gate oxide thickness and gate work function materials add more flexibility for tuning of DGMOSFET device threshold voltage and minimizing SCEs which are not available in tied gate symmetric DGMOSFETs.
机译:DGMOSFET的非对称和独立栅极特性最近在纳米级应用中得到了探索。本文基于DGMOSFET的独立栅极,搭接下的栅极S / D和不对称(前后栅极氧化物厚度,栅极功函数和栅极偏置)特性,研究了短沟道效应的最小化。提出了具有非对称,独立栅极特性的欠重叠DGMOSFET的阈值电压,阈值电压滚降和DIBL效应的新型分析模型,并通过数值仿真结果进行了验证。总体而言,结果表明,通过适当调整背栅偏置,背栅氧化层厚度和栅极功函数材料,可将DGMOSFET的门下重叠特性和不对称性引入,为DGMOSFET器件阈值电压的调整和最小化SCE提供了更大的灵活性。栅极对称DGMOSFET。

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