A sample-and-hold circuit implemented with mixed MOS transistor channel length technique used in 16-bit 100-MS/s A/D converter

摘要

This paper discusses the design and implementation of a sample-and-hold circuit integrated into a high-speed and high-resolution A/D converter. In order to achieve the required speed and resolution, mixed MOS transistor channel length amplifier is used. The sample-and-hold circuit processes a differential 2.5-Vp-p output signal swing and achieves 16-bit linearity with sampling frequency up to 100 MHz. Under these conditions, the total power consumption is 300 mW given by a single 3.3-V supply. The A/D converter is fabricated in a standard 0.35- µ m CMOS process technology, achieves 95.33-dBc spurious free dynamic range, 75.75-dBc signal-to-noise ratio for a 10.1-MHz input at −0.9dBFS at full sampling rate.