(54) Title: METHOD AND SYSTEM FOR ACCELERATED ANALOG TO DIGITAL CONVERSION (57) Abstract: Techniques for accelerated processing associated with, analog to digital signal conversion are disclosed. Accelerat¬ed processing is provided for sample-and-hold and track-and-hold circuits used with analog to digital converters in various em¬bodiments. An abbreviated sampling state, an abbreviated reset state, or both are employed in various embodiments. By accelerat¬ing processing so as to avoid the need for waiting for a signal to settle within a predetermined tolerance, errors of different types may be incurred. Such errors are determined during calibration and stored for future retrieval and error compensation. Techniques for online and offline calibration are disclosed, whereby calibration may or may not impact normal signal conversion processing. Techniques disclosed herein find broad applicability in analog to digital conversion and yield faster processing in a variety of con¬texts.

摘要

pTechniques for accelerated processing associated with analog to digital signal conversion are disclosed. Accelerated processing is provided for sample-and-hold and track-and-hold circuits used with analog to digital converters in various embodiments. An abbreviated sampling state, an abbreviated reset state, or both are employed in various embodiments. By accelerating processing so as to avoid the need for waiting for a signal to settle within a predetermined tolerance, errors of different types may be incurred. Such errors are determined during calibration and stored for future retrieval and error compensation. Techniques for online and offline calibration are disclosed, whereby calibration may or may not impact normal signal conversion processing. Techniques disclosed herein find broad applicability in analog to digital conversion and yield faster processing in a variety of contexts./p [WO2011019580A1]