Device Technology for High Performance Monolithic Sample-and-Hold Circuits.

摘要

Development of devices for a monolithic sample and hold on a single chip was undertaken. Process developments were conducted to incorporate a p channel JFET and Schottky diodes into a high speed monolithic process. A test chip was designed and evaluated. The chip included test devices, test circuits and a complete sample-and-hold. The test results indicated that the devices were acceptable for sample and hold circuits. The test results of the sample and hold indicated 7 bit performance at sample rates of up to 50 Msps. (Author)