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A novel cylinder-type MIM capacitor in porous low-k film (CAPL) for embedded DRAM with advanced CMOS logics

机译:一种新颖的圆柱型MIM电容器,用于多孔低k膜(CAPL),用于具有先进CMOS逻辑的嵌入式DRAM

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A novel cylinder-type metal-insulator-metal (MIM) capacitor in porous low-k film (CAPL) is proposed for embedded DRAMs (eDRAMs). The CAPL removes long bypass-contacts (BCT) with high resistance, which have been used to connect transistors with Cu interconnects by way of the MIM capacitor layer. A key technical challenge for the CAPL integration is control of pore structure in the low-k film to avoid metal contamination during the gas-phase deposition of the MIM electrode (BE) on the porous low-k film. A molecular-pore-stack (MPS) SiOCH film (k=2.5) with very small pores (0.4 nm-diameter) is found to be the best candidate for the CAPL structure, applicable to eDRAM with high performance logics for 28 nm-node and beyond.
机译:提出了一种新型的圆柱形低介电常数薄膜(CAPL)圆柱型金属-绝缘体-金属(MIM)电容器,用于嵌入式DRAM(eDRAM)。 CAPL消除了具有高电阻的长旁路触点(BCT),该触点已用于通过MIM电容器层连接具有Cu互连的晶体管。 CAPL集成的一项关键技术挑战是控制低k膜中的孔结构,以避免在MIM电极(BE)气相沉积在多孔低k膜上的过程中金属污染。发现具有很小孔(直径0.4 nm)的分子孔堆叠(MPS)SiOCH膜(k = 2.5)是CAPL结构的最佳选择,适用于具有28 nm节点高性能逻辑的eDRAM超越。

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