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MAPPER: High throughput maskless lithography

机译:MAPPER:高通量无掩模光刻

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Maskless electron beam lithography, or electron beam direct write, has been around for a long time in the semiconductor industry and was pioneered from the mid-1960s onwards. This technique has been used for mask writing applications as well as device engineering and in some cases chip manufacturing. However because of its relatively low throughput compared to optical lithography, electron beam lithography has never been the mainstream lithography technology. To extend optical lithography double patterning, as a bridging technology, and EUV lithography are currently explored. Irrespective of the technical viability of both approaches, one thing seems clear. They will be expensive.MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing with high speed optical data transport for switching the electron beams. In this way optical columns can be made with a throughput of 10-20 wafers per hour. By clustering several of these columns together high throughputs can be realized in a small footprint. This enables a highly cost-competitive alternative to double patterning and EUV alternatives. In 2007 MAPPER obtained its Proof of Lithography milestone by exposing in its Demonstrator 45 nm half pitch structures with 110 electron beams in parallel, where all the beams where individually switched on and off .In 2008 MAPPER has taken a next step in its development by building several tools. The objective of building these tools is to involve semiconductor companies to be able to verify tool performance in their own environment. To enable this, the tools will have a 300 mm wafer stage in addition to a 110-beam optics column. First exposures at 45 nm half pitch resolution have been performed and analyzed. On the same wafer it is observed that all beams print and based on analysis of 11 beams the CD for the different patterns is within 2.2 nm from target and the CD uniformity for the different patterns is better than 2.8 nm.
机译:无掩模电子束光刻或电子束直接写入,在半导体行业已经长时间长期以来,并从20世纪60年代中期开始开展。该技术已被用于掩模写入应用以及设备工程以及在某些情况下芯片制造。然而,由于其与光学光刻相比的吞吐量相对较低,电子束光刻从未成为主流光刻技术。为了延伸光学光刻双重图案,作为桥接技术,目前探讨了EUV光刻。无论两种方法的技术可行性如何,有一件事似乎很清楚。他们会很贵。 映射光刻正在基于具有高速光学数据传输的基于大规模平行的电子束写入的掩模光刻技术,用于切换电子束。以这种方式,可以通过每小时10-20个晶片的吞吐量进行光学柱。通过将多个列中的群集聚集在一起,可以在小占地面积中实现高吞吐量。这使得具有高度成本竞争的替代方案来双重图案化和EUV替代品。在2007年,Mapper通过并行地具有110个电子束的示范器45nm半间距结构,获得了光刻里程碑的证明,并行地,其中单独接通和断开的所有光束。 在2008年,Mapper通过构建了几个工具,在其开发中进行了下一步。建立这些工具的目标是涉及半导体公司能够在自己的环境中验证工具性能。要启用此功能,除了110梁光学柱外,工具还将具有300 mm晶片级。已经进行并分析了45nm半间距分辨率的第一曝光。在相同的晶片上观察到,所有光束打印和基于11个光束的分析,不同图案的CD在2.2nm内,不同图案的CD均匀性优于2.8nm。

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