Effect of Layout Orientation on the Performance and Reliability of High Voltage N-LDMOS in Standard Submicron Logic STI CMOS Process

摘要

N-LDMOS (N-channel Laterally Diffused Drain MOS-FET) fabricated in a standard CMOS process is used to provide relatively high-voltage (HV～12V) capability without any extra process steps [1-4]. It is widely used in smart power circuits that combine a HV output with low power control circuitry. Characterization, modeling, optimization [3-4] and reliability of N-LDMOS devices [5-6] were previously reported mainly on devices fabricated in technology nodes down to 0.35 μm with LOCOS isolation. However, there is very little information available for LDMOS devices with technologies below 0.35 μm using STI isolation [7-8]. In this work, we investigated the typical layout geometry dependence of device drain current leakage, drain breakdown and on-state current characteristics fabricated in a standard logic 0.18μm and 0.25μm process. Furthermore, for the first time, a dependence on layout orientation and its effect on hot-carrier injection (HCI) reliability are reported.