A reduced mask count process for the production of mixed voltage CMOS with high performance transistors and high reliability I / O transistors

摘要

A mixed voltage CMOS process for high reliability and high performance core transistors and input-output transistors with reduced mask steps. A gate stack (30) is formed over the silicon substrate (10). Ion implantation is performed of a first species and a second species to produce the doping profiles (70, 80, 90, 100) in the input-output transistors. IMAGE IMAGE