Relationship between profile of stress generated interface traps and degradation of submicron LDD MOSFET'S

摘要

By relating the complete spatial interface trap profile to the variation of electrical parameters in n-channel LDD and FOND MOSFET's, we clarify the respective role of defects above the channel and the LDD region. We show that the saturation of the series resistance increase is due to the leveling off of the rate of interface trap generation and not to the self-limiting impact of such defects on the series resistance. The importance of the choice of the parameter, used to estimate the lifetime is demonstrated.