A comparison of conventional single-chip on high-density printed wiring board (PWB) packaging with both ceramic and silicon-substrate multichip module (MCM) strategies is presented. Both approaches are assessed given current state-of-the-art manufacturing capabilities and projections for the foreseeable future. The computer system used as the basis to investigate the relative impact of these packaging approaches is representative of a current workstation with a reduced instruction set computing (RISC) architecture. This study was conducted with AUDiT Version 4.2, an innovative simulation tool for evaluating the physical design of electronic systems. It is demonstrated that the maximum efficiency of the conventional single-chip PGA module on PWB packaging of state-of-the-art RISC workstations, such as the IBM RS/6000, is only about 14%. The addition of signal layers may improve speed performance for a given PWB design rule, but not beyond the PGA package tiling limit constraint. Introduction of multichip packaging greatly increases processor speed and dramatically reduces the overall system size.
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