Ultra-thin packages with embedded actives for high functional density have become strategically important with fast growing market for portable electronics. 3D Packaging Research Center at Georgia Tech is pioneering a chip-last approach for die embedding using adhesively bonded copper bumps to enable ultra-fine pitch chip-to-package interconnections. This paper presents three advancements over the adhesive bonding technology demonstrated previously- 1) A novel method to perform chip-last at panel-level, leading to 10–15× reduction in assembly time per die, 2) Improved 2-step assembly process to achieve simultaneous die embedding and cavity planarization, and 3) Adhesive bonding of high I/O die. To demonstrate high throughput assembly, x-ray and electrical yield results for an 8–10 dies, simultaneously bonded on a 3" × 3" panel with high accuracy have been discussed. The assembly process modification yielded planarization of the gap between the die and cavity wall to <1μm. Electrical yield of adhesively bonded large die with ∼800 I/Os has also been discussed. These technology advancements aim to address some of the key limitations of conventional adhesive based assemblies, thus making chip-last adhesive bonding with low profile copper-to-copper interconnections a robust chip embedding solution for next-generation of highly integrated heterogeneous subsystems.
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