In this work we examine the problem of the nonlinear output characteristics of tunnel FETs, and the related small drain conductance at low drain voltage, which prevents rail-to-rail logic operation and severely degrades the device dynamic properties compared with standard CMOS FETs. The problem is investigated with the help of an analytical model which highlights the constraints of the device design by splitting the effects of the tunneling probability from the density of states in the source, channel and drain, and makes it possible to design a nanowire TFET by an appropriate selection of the material, nanowire size and degeneracy levels in the source and drain regions. So doing, we remove the above characteristics' feature and recover a large drain conductance without degrading the subthreshold slope. The optimized device is numerically simulated using the k·p model, whose results are in fair agreement with the analytical one.
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机译:在这项工作中,我们检查隧道FET的非线性输出特性的问题,以及低漏极电压下的相关小漏极电导,这防止了轨到轨道逻辑操作,并与标准CMOS FET相比严重降低了器件动态特性。借助于分析模型研究了问题,该模型通过将隧道概率与源极,通道和漏极密度的效果分裂来突出显示装置设计的约束,并且可以通过设计纳米线TFET来实现an appropriate selection of the material, nanowire size and degeneracy levels in the source and drain regions.因此,我们这样做,我们去除上述特征的特征,并在不降低亚阈值斜率的情况下恢复大的漏极电导。使用K·P型号进行数值模拟优化的设备,其结果与分析1相协议。
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