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Board level flat and vertical drop impact reliability for wafer level chip scale package

机译:板级平坦和垂直下降的晶圆级芯片尺度包的可靠性

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摘要

In this paper, a comprehensive modeling is carried out to investigate the dynamic behaviors of WL-CSP subjected to both flat and vertical drop impacts. The non-linear dynamic properties include solder, Cu pad and the metal stacking under the UBM. Both of the JEDEC standard flat drop test and the vertical drop test modeling for different solder bump height are studied. The results showed that, in the JEDEC standard flat drop test, Stress of the corner balls at each WL-CSP is much higher than the balls in other locations on the same components. The results showed the vertical drop stress is lower than the flat drop stress. The result of JEDEC standard flat drop test modeling showed that the higher solder joint of the WL-CSP can result in lower plastic impact energy but higher tensile (first principal) stress S1 at solder joint.
机译:在本文中,进行了综合建模,以研究WL-CSP对垂直和垂直下降影响的WL-CSP的动态行为。非线性动态特性包括焊料,Cu焊盘和UBM下的金属堆叠。研究了JEDEC标准平面测试和不同焊料凸块高度的垂直滴测试建模。结果表明,在JEDEC标准平面测试中,每个WL-CSP的角球的应力远高于相同部件上的其他位置的球。结果表明垂直落液应力低于平坦跌落应力。 JEDEC标准平面滴测测试建模的结果表明,WL-CSP的较高焊点可导致焊接接头处的较低塑料冲击能量但较高的拉伸(第一主)应力S1。

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