On-Chip Isolation in Wafer-Level Chip-Scale Packages: Substrate Thinning and Circuit Partitioning by Trenches

摘要

Introduction of WLCSP technology enables implementation of novel techniques for on-chip isolation. When a core-technology silicon substrate is bonded to a supporting glass wafer, it can be thinned and/or trenched and its mechanical integrity is not lost. In this paper, substrate thinning and circuit partitioning by complete substrate trenching are introduced and investigated for substrate crosstalk suppression. Silicon substrates having thickness of 20 - 525 μm with and without through-substrate trenches (trench width 0-100 μm) were analyzed and compared to reference structures without any isolation and/or isolation based on guard ring structures. The simulation results obtained show that both techniques are effective for substrate crosstalk suppression. The achievable isolation level at given frequency range can be tuned by adjusting the applied trench width.