Wire Loop Development for Advanced PBGA Packages With Multiple Rows of Bonding Fingers and Power-Ground Rings

摘要

For ASIC devices with 1000+ pad count packaged in advanced PBGA with multiple rows of power and ground rings and multiple row of staggered bonding fingers, wire crossing is un-avoidable. To prevent crossing wires from touching each other, wire loop profile control is critical. This paper described a method to model the behavior of loop profile and presented a model for 220 mil long gold wire. This model can forward predict loop profile from a given set of bonding parameters. The same model together with desirability function can backward predict the optimized set of bonding parameters from a given loop profile by design. The combination of forward and backward method can predict process window for a desirable loop profile.