Development of a 3D-Chip Scale Package (CSP) using Chip in Polymer Technology

摘要

This paper deals with a new technique that isused for fabricating thin chip scale packages(Fig. 1). Thin chips (~50μm) with electrolessNi/Cu bumps are die bonded on a standardprinted circuit board (PCB). The thin chips areembedded in a photosensitive dielectric epoxyand were contacted by electroless copperdeposition (Fig. 2). This embedding technologyis called “Chip in Polymer”.The materials chosen for this process arestandard materials from the PCB industry. Thisallows a relatively low-cost and easy handlingof the materials. In the process two lithographyprocess steps with glass masks are needed.The first approach is the design of a 3D-CSP,were three thin packages are stacked on top each other in order to achieve a highpackaging density (Fig. 3). For the firstinvestigation a Flat-CSP-demonstrator hasbeen realized. The following processdescription apply to the Flat-CSP.Additional a test board has been created. Onthis board the Flat-CSP could be soldered andtested.The basic of the construction is a 10x10cm2FR4 board with a thickness of 500μm. On thissubstrate 14 thin chips were die bonded usinga manual flip chip bonder. Eight of the chips at the assembly site of theboard are for the Flat-CSP. Beside Flat-CSPstructures there are other geometrical andelectrical test structures (Fig. 4). The chips arebonded using a low viscosity underfiller . Thethickness of the glue layer is 10-15μm.