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Dopant Activation and Leakage Current Aspects of SDE/Halo CMOS Junctions Measured with Non-contact Junction Photo-Voltage Methods

机译：非接触结光电电压方法测量的SDE / Halo CMOS结的掺杂物激活和漏电流方面

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The thin depletion layers and high leakage currents for shallow SDE/halo profiles rule out the continued use of direct contact sheet resistance probes. Non-contact probes based on junction photo-voltage (JPV) measurements provide accurate sheet resistance

机译：较薄的耗尽层和用于浅SDE /晕圈轮廓的高泄漏电流排除了继续使用直接接触薄层电阻探针的情况。基于结型光电压（JPV）测量的非接触式探头可提供准确的薄层电阻

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《Junction Technology, 2007 International Workshop on 》|2007年|P.43-46|共4页
会议地点 KyotoJapan
作者
Current; M.; Faifer; V.; Halim; J.; Ohno; N.;
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CMOS integrated circuits; doping profiles; leakage currents; semiconductor doping; semiconductor junctions; voltage measurement; SDE/halo CMOS junctions; Si; Si - Interface; dopant activation; junction leakage current; noncontact junction photovoltage methods; nonco;

机译：CMOS集成电路；掺杂分布漏电流半导体掺杂半导体结；电压测量SDE / halo CMOS结； ; Si-接口；掺杂剂激活结漏电流；非接触结光电压方法；诺科;

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1. Junction Depth Dependence of the Gate Induced Drain Leakage in Shallow Junction Source/Drain-Extension Nano-CMOS [J] . Seung-Hyun SONG, Jae-Chul KIM, Sung-Woo JUNG, IEICE Transactions on Electronics . 2008 ,第5期

机译：浅结源极/漏极扩展纳米CMOS中栅极感应的漏极泄漏的结深度依赖关系
2. New Method for Evaluating Electric Field at Junctions of DRAM Cell Transistors by Measuring Junction Leakage Current [J] . Mori Y., Kimura S., Yamada R. IEEE Transactions on Electron Devices . 2009 ,第2期

机译：通过测量结漏电流评估DRAM单元晶体管结的电场的新方法
3. Influence of halo implant on leakage current and sheet resistance of ultrashallow p-n junctions [J] . V. N. Faifer, D. K. Schroder, M. I. Current, Journal of Vacuum Science & Technology . 2007 ,第5期

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4. Dopant Activation and Leakage Current Aspects of SDE/Halo CMOS Junctions Measured with Non-contact Junction Photo-Voltage Methods [C] . Michael Current, Vladimir Faifer, Jefrri Halim, International Workshop on Junction Technology . 2007

机译：用非接触结光电电压测量的SDE /晕CMOS结的掺杂剂激活和漏电流方面
5. Low resistivity contact methodologies for silicon, silicon germanium and silicon carbon source/drain junctions of nanoscale CMOS integrated circuits. [D] . Alptekin, Emre. 2009

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机译：接触塞沉积条件对多级CMOS逻辑互连器件中结漏电流和接触电阻的影响
7. CMOS Integration using Low Thermal Budget Dopant-Segregated Metallic S/D Junctions on Thin-Body SOI [O] . G. Larrieu A, E. Dubois B, D. Ducatteau B 2016

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Dopant Activation and Leakage Current Aspects of SDE/Halo CMOS Junctions Measured with Non-contact Junction Photo-Voltage Methods

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