Stacked Array Packaging: A Flex Based IC Packaging Solution for Single and 3D Multiple Die Applications

摘要

The challenge manufactures face when competing in the world marketplace is to offer a product that will meet all performance and functionality expectations without increasing product size or cost. Increased electronic functionality can be achieved through the development of more complex silicon integration but that route generally requires a great deal of capital resources and an excessive amount of time. Multiple-die package concepts are often proving superior to the system-on-chip alternative because it minimizes risk and has the potential for economically integrating several different but complementary functions. The information presented in this paper will review several existing package-on-package configurations and introduce a new substrate fabrication process developed to improve IC package density and circuit routing efficiency. In addition, the basic package assembly methodology will be described and examples of high density stacked memory and mixed function variations shown. In keeping with IPC presentation guidelines it should be noted that a portion of the technical information presented focuses on unique fabrication processes developed for the substrate and are a licensed technology covered by several US and foreign patents.