首页> 外文会议>IPC Printed Circuits Expo, Apex, and the Designers Summit; 20070220-22; Los Angeles,CA(US) >The Whisker Growth Investigation of IC Packaging on the PC Board Assembly
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The Whisker Growth Investigation of IC Packaging on the PC Board Assembly

机译:PC板组件上IC封装的晶须生长调查

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The whisker concern has been greatly affecting lead free RoHS conversion confidence in the lead frame packages, particularly for high end product conversion. Although plenty of related study in E4 and iNEMI have directed standard whisker testing conditions and measurement methods, the practical whisker performance data in service life is still very small due to numerous extra factors involved from surface mounting and waving soldering. Most of the literature on Tin (Sn) whiskers study are test results based at the component level in storage or reflow preconditioning to simulate backward and forward conversion in service life. However, for practical Sn-whisker issues, it is necessary to consider the entire structure, i.e., the component characteristics, solder joint, PCB and process effect. In this study, matt Sn plated packages with Cu and Alloy 42 based in PLCC, PDIP, LQFP and TSOP were subject to lead free surface mounting and wave soldering on PCBs with OSP surface finish, followed by TCT (-55 to 85℃) 1000 cycle, THT (60℃/90%RH) 3000hrs and ambient condition 3000hrs to investigate whisker growth propensity. Whisker growth on the PCB after reflow simulation and separate from the component level was examined to understand whether the whisker risk will be reduced or raised because of factors such as the matt Sn structure, lead frame base, reflow profile and solder paste wetting behavior. Furthermore, SnPb and SnBi plated 4 types of the same package types as above were used as controls for whisker growth comparison. Additionally, corrosion phenomenon due to higher temperature THT testing to correlate to whisker growth after the surface mounting condition will be explored with FIB analysis as well.
机译:晶须问题极大地影响了引线框架封装中无铅RoHS转换的信心,特别是对于高端产品转换。尽管有关E4和iNEMI的大量相关研究都针对标准晶须测试条件和测量方法,但由于表面安装和波峰焊涉及许多额外因素,使用寿命内的实际晶须性能数据仍然很小。有关锡(Sn)晶须研究的大多数文献都是基于存储或回流预处理中组分水平的测试结果,以模拟使用寿命中的向前和向后转换。但是,对于实际的锡晶须问题,有必要考虑整个结构,即部件特性,焊点,PCB和工艺效果。在这项研究中,对基于PLCC,PDIP,LQFP和TSOP的含铜和42合金的无光泽锡镀层封装进行无铅表面安装和波峰焊接在具有OSP表面处理的PCB上,然后进行TCT(-55至85℃)1000循环,THT(60℃/ 90%RH)3000hrs和环境条件3000hrs考察晶须的生长倾向。考察了回流模拟后PCB上晶须的生长情况,并从元件水平上分离出晶须,以了解是否会由于诸如无光泽锡结构,引线框架基础,回流曲线和焊膏润湿行为等因素而降低或增加晶须风险。此外,将与上述相同封装类型的SnPb和SnBi镀覆的4种类型用作晶须生长比较的对照。此外,还将通过FIB分析探索由于高温THT测试导致的与表面安装条件后晶须生长相关的腐蚀现象。

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