首页> 外文会议>International Workshop on Junction Technology; 20060515-16; Shanghai(CN) >Device Performance Evaluation of PMOS Devices Fabricated by B2H6 PIII/PLAD Process on Poly-Si Gate Doping
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Device Performance Evaluation of PMOS Devices Fabricated by B2H6 PIII/PLAD Process on Poly-Si Gate Doping

机译:B2H6 PIII / PLAD工艺制造的多晶硅栅掺杂PMOS器件的器件性能评估

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摘要

It has been shown that the PIII/PLAD poly-Si gate doping process offers unique advantages over conventional beam line systems, including system simplification, lower cost, higher throughput, and device performance equivalence or improvement. PMOS devices fabricated by a B2H6/H2 PIII/PLAD process on P + poly-gate doping are intensively evaluated in this paper. In addition to higher throughput, PMOS devices fabricated by a PLAD process showed an equivalent electrical performance to those fabricated by conventional beam line ion implantation, including similar poly-Si gate resistance and depletion, threshold and sub-threshold characteristics, drive current, and gate-oxide integrity.
机译:已经显示出,PIII / PLAD多晶硅栅极掺杂工艺相对于传统的束线系统具有独特的优势,包括系统简化,成本更低,产量更高以及等效或改进的器件性能。本文对采用P2 +栅掺杂的B2H6 / H2 PIII / PLAD工艺制造的PMOS器件进行了深入评估。除了更高的吞吐量外,通过PLAD工艺制造的PMOS器件还具有与常规束线离子注入制造的器件相同的电性能,包括相似的多晶硅栅极电阻和耗尽,阈值和亚阈值特性,驱动电流和栅极-氧化物完整性。

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