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Highly conducting doped poly-Si deposited by hot wire CVD and its applicability as gate material for CMOS devices

机译:通过热线CVD沉积的高导电掺杂多晶硅及其作为CMOS器件的栅极材料的适用性

摘要

Highly conducting p- and n-type poly-Si:H films were deposited by hot wire chemical vapor deposition (HWCVD) using SiH4+H2+B2H6 and SiH4+H2+PH3 gas mixtures, respectively. Conductivity of 1.2×102 (Ω cm)−1 for the p-type films and 2.25×102 (Ω cm)−1 for the n-type films was obtained. These are the highest values obtained so far by this technique. The increase in conductivity with substrate temperature (Ts) is attributed to the increase in grain size as reflected in the atomic force microscopy results. Interestingly conductivity of n-type films is higher than the p-type films deposited at the same Ts. To test the applicability of these films as gate contact Al/poly-Si/SiO2/Si capacitor structures with oxide thickness of 4 nm were fabricated on n-type c-Si wafers. Sputter etching of the poly-Si was optimized in order to fabricate the devices. The performance of the HWCVD poly-Si as gate material was monitored using C–V measurements on a MOS test device at different frequencies. The results reveal that as deposited poly-Si without annealing shows low series resistance.
机译:通过热丝化学气相沉积(HWCVD)分别使用SiH4 + H2 + B2H6和SiH4 + H2 + PH3气体混合物沉积高导电p型和n型多晶硅:H膜。对于p型膜,电导率为1.2×102(Ωcm)-1;对于n型膜,电导率为2.25×102(Ωcm)-1。这些是迄今为止通过该技术获得的最高值。电导率随基材温度(Ts)的增加归因于原子力显微镜结果中晶粒尺寸的增加。有趣的是,n型膜的电导率高于在相同Ts下沉积的p型膜。为了测试这些膜作为栅极接触的适用性,在n型c-Si晶片上制造了氧化物厚度为4 nm的Al / poly-Si / SiO2 / Si电容器结构。为了制造器件,对多晶硅的溅射蚀刻进行了优化。 HWCVD多晶硅作为栅极材料的性能使用MOS测试设备上不同频率的C–V测量进行监控。结果表明,未经退火的沉积多晶硅显示出低串联电阻。

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