Two-Dimensional Model for the Subthreshold Slope in Deep-Submicron Fully-Depleted SOI MOSFET's

机译：深亚微米全耗尽SOI MOSFET的亚阈值斜率的二维模型

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A 2D analytical model for the calculation of the subthreshold slope has been derived for deep-submicron Fully-Depleted SOI MOSFET's using a Green's function solution technique. The accuracy of the equations has been verified by a 2D numerical device simulator. It is shown that the analytically derived model for the subthreshold slope is in good agreement with 2D numerical simulation data.

机译：使用格林函数求解技术，为深亚微米全耗尽SOI MOSFET导出了用于计算亚阈值斜率的二维分析模型。方程的准确性已通过2D数值设备模拟器进行了验证。结果表明，亚阈值斜率的解析推导模型与二维数值模拟数据吻合良好。

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《International Conference on Simulation of Semiconductor Devices and Processes, SISPAD '01, Sep 5-7, 2001, Athens》|2001年|p.238-241|共4页
会议地点 Athens(GR);Athens(GR)
作者
Hans van Meer; Kristin De Meyer;
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作者单位

STDI division, IMEC, Kapeldreef 75, B-3001 Leuven, Belgium;

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原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
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专利

1. Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs [J] . Gopi Krishna Saramekala, Abirmoya Santra, Mirgender Kumar, Journal of Computational Electronics . 2014,第2期

机译：短沟道双金属栅（DMG）全耗尽型凹源极/漏极（Re-S / D）SOI MOSFET的分析亚阈值电流和亚阈值摆幅模型
2. Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SOI MOSFETs down to 0.1 mu m gate length [J] . Joachim H.-O., Yamaguchi Y. IEEE Transactions on Electron Devices . 1993,第10期

机译：栅极长度低至0.1μm的超薄膜SOI MOSFET亚阈值斜率的仿真和二维分析建模
3. AN ANALYTICAL (CLASSICAL) SUBTHRESHOLD BEHAVIOR MODEL FOR SYMMETRICAL FULLY-DEPLETED SOI DOUBLE-GATE MOSFET's [J] . Te-Kuang Chiang Journal of the Chinese Institute of Engineers. Series A . 2004,第2期

机译：对称全耗尽SOI双栅极MOSFET的解析（经典）亚阈值行为模型
4. Two-Dimensional Model for the Subthreshold Slope in Deep-Submicron Fully-Depleted SOI MOSFET's [C] . Hans van Meer, Kristin De Meyer International Conference on Simulation of Semiconductor Devices and Processes . 2001

机译：深度耗尽SOI MOSFET亚亚亚丘坡二维模型
5. Design and modeling of non-uniformly doped deep-submicron pocket MOSFETs for low-voltage low-power applications [D] . Pang, Yon-Sup. 2000

机译：用于低压低功率应用的非均匀掺杂深亚微米口袋MOSFET的设计和建模
6. Study of a hysteresis window of FinFET and fully-depleted silicon-on-insulator (FDSOI) MOSFET with ferroelectric capacitor [O] . Chankeun Yoon, Seungjun Moon, Changhwan Shin -1

机译：FinFET和带铁电电容器的全耗尽绝缘体上硅（FDSOI）MOSFET的磁滞窗口研究
7. Modeling and simulation of subthreshold characteristics of fully-depleted recessed-source/drain UTB SOI MOSFETs including substrate induced surface potential effects [O] . Kumar Ajit 2014

机译：完全耗尽的源极/漏极UTB SOI MOSFET亚阈值特性的建模和仿真，包括衬底引起的表面电势效应
8. DLTS and Dynamic Transconductance Analysis of Deep-Submicron Fully-Depleted SOIMOSFETs [R] . Ioannou, D. E. 1993

机译：深亚微米全耗尽sOImOsFET的DLTs和动态跨导分析

Two-Dimensional Model for the Subthreshold Slope in Deep-Submicron Fully-Depleted SOI MOSFET's

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