High Mobility Nanocrystalline Silicon Thin Film Transistors for CMOS on Plastic Substrates

摘要

P and n-channel thin film transistors were made from PECVD deposited nanocrystalline silicon at process temperatures as low as 150℃. A staggered top gate, bottom source/drain geometry ensures that the channel is the last-to-grow layer and avoids damage by plasma etching. We introduce a 50-nm ～ 75-nm thick intrinsic nc-Si:H seed layer underneath the whole TFT structure to develop the crystalline structure of the channel layer. The field effect mobilities obtained are ～0.2 cm~2V~(-1)s~(-1) for holes and ～ 45 cm~2V~(-1)s~(-1) for electrons. This result demonstrates the feasibility of directly-deposited and CMOS capable silicon TFT technology on plastic substrates.