Impact of BEOL, multi-fingered layout design, and gate protection diode on intrinsic MOSFET threshold voltage mismatch

机译：BEOL，多指布局设计和栅极保护二极管对本征MOSFET阈值电压失配的影响

获取原文

页面导航

摘要
著录项
引文网络
相似文献
相关主题

摘要

Continued scaling down of MOSFETs, compounded with limitation in process variation control capabilities, has made MOSFET mismatch more significant for advanced technologies. In order to prevent over compensating for MOSFET mismatch in design margin, it is

机译：MOSFET的不断缩小，加上工艺变化控制功能的局限性，使得MOSFET失配对于先进技术变得更加严重。为了防止过度补偿MOSFET在设计裕度方面的失配，它是

著录项

来源
《Electron Devices and Solid- State Circuits, 2007 IEEE Conference on》|2007年|P.1059-1062|共4页
会议地点 TainanTaiwan
作者
Lim; G.H.; Zhou; X.; Khu; K.; Yoo; Y.K.; Poh; F.; See; G.H.; Zhu; Z.M.; Wei; C.Q.; Lin; S.H.; Zhu; G.J.;
展开▼
作者单位

展开▼
会议组织
原文格式 PDF
正文语种
中图分类
关键词
MOSFET; semiconductor diodes; BEOL; back end of line; gate protection diode; intrinsic MOSFET threshold voltage mismatch; multi-fingered layout design; process variation control;

机译：MOSFET;半导体二极管； BEOL;行尾；栅极保护二极管；固有MOSFET阈值电压失配;多指布局设计；过程变化控制;

相似文献

外文文献
中文文献
专利

1. Hot carrier degradation behavior in SOI dynamic-threshold-voltage nMOSFET's (n-DTMOSFET) measured by gated-diode configuration [J] . Ru Huang, Jinyan Wang, Jin He, Microelectronics & Reliability . 2003,第5期

机译：通过栅二极管配置测量的SOI动态阈值电压nMOSFET（n-DTMOSFET）中的热载流子退化行为
2. Analytical threshold voltage model with TCAD simulation verification for design and evaluation of tri-gate MOSFETs [J] . Yawei Jin, Chang Zeng, Lei Ma, Solid-State Electronics . 2007,第3期

机译：具有TCAD仿真验证的分析阈值电压模型，用于三栅极MOSFET的设计和评估
3. Impact of Using Double-Patterning Versus Single-Patterning on Threshold Voltage $(V_{rm TH})$ Variation in Quasi-Planar Tri-Gate Bulk MOSFETs [J] . Shin C., Park I.J. Electron Device Letters, IEEE . 2013,第5期

机译：使用双模式和单模式对阈值电压的影响 $（V_ {rm TH}）$ 准-平面三栅极体MOSFET
4. Impact of BEOL, multi-fingered layout design, and gate protection diode on intrinsic MOSFET threshold voltage mismatch [C] . Lim G. H., Zhou X., Khu K., IEEE Conference on ELectron Devices and Solid-State Circuits . 2007

机译：BEOL，多指布局设计和栅极保护二极管对内在MOSFET阈值电压不匹配的影响
5. Comparative Analysis of Simulation of Trap Induced Threshold Voltage Fluctuations for 45 nm Gate Length n-MOSFET and Analytical Model Predictions. [D] . Ashraf, Nabil Shovon. 2011

机译：45 nm栅极长度n-MOSFET陷阱引起的阈值电压波动仿真的比较分析和分析模型预测。
6. 3D Numerical Simulation of a Z Gate Layout MOSFET for Radiation Tolerance [O] . Ying Wang, Chan Shan, Wei Piao, 2018

机译：Z栅极布局MOSFET的3D数值模拟
7. Intrinsic Nonlinearities and Layout Impacts of 100 V Integrated Power MOSFETs in Partial SOI Process [O] . Fan Lin, Knott Arnold, Jørgensen Ivan Harald Holger 2016

机译：部分sOI工艺中100 V集成功率mOsFET的本征非线性和布局影响
8. Influence of the Polysilicon Gate on the Random Dopant Induced Threshold Voltage Fluctuations in Sub 100 nm MOSFETS with Thin Gate Oxides [R] . Asenov, Asen, Saini, S. 2000

机译：多晶硅栅极对具有薄栅氧化层的亚100nm mOsFET中随机掺杂诱导阈值电压波动的影响

Impact of BEOL, multi-fingered layout design, and gate protection diode on intrinsic MOSFET threshold voltage mismatch

摘要

著录项

引文网络

相似文献

相关主题

期刊订阅