Electrical characterization of Ge-pFETs with HfO/TiN metal gate: Review of possible defects impacting the hole mobility

摘要

Recently, best 65 nm Ge pMOSFET performance has been reported with a standard Si CMOS HfO_2 gate stack module (1). In this contribution, we investigated in more detail how device performance, especially the hole mobility, depends on the characteristics of layers featuring the gate dielectric (HfO_2, SiC>2 and the Si cap layer). We found that many point defects are involved in the mobility control. We specifically highlight the role of defects linked to the Si cap integration. A critical Si thickness is also extracted, separating two important regimes. We finally report the difference in hole-mobility-limiting mechanisms between Ge devices integrating two different Epi-Si passivation schemes. Based on low temperature measurements, the promising SisHs process shows an additional coulomb scattering mechanism compared to SiH4.