Asynchronous techniques for digital MESFET gallium arsenide circuits

摘要

Abstract: There are many applications where ultra-fast digital arithmetic circuits are required. At ultra-high speeds a considerable part of power is dissipated within a clock generation and distribution syste. At the same time, at gigahertz frequencies the clock skew becomes a factor limiting the speed of the system. This paper presents a design methodology for highly pipelined, self-timed circuits and systems suitable for multimedia applications using Gallium Arsenide MESFET as the base technology implementation of latched logic design style (PDLL, LCFL). The use of latched logic together with the absence of the global clock provides for low power dissipation while maintaining very high speed of the system. The main advantage of the latched structure is provided by the feedback which ensures that the nose margin is higher than for a simple Direct Coupled FET Logic gate. This enables to use serial connections of the E-type transistors in the pull-down section. Therefore, in GaAs latched logic it is possible to implement logic gates based on the AND function which have several control inputs and that they generate at least one control signal for handshaking. For the typical 4- phase handshaking protocol the input signals are enable and start and the required generated signal is Done. In the paper the appropriate modifications of the handshaking protocol to accommodate the properties of the latched logic GaAs circuits is presented an the inherent latching property of LCFL is exploited to eliminate latches separate from the logic blocks in the classic pipeline. Several circuit examples demonstrate the advantages of the proposed circuit techniques. !13