首页> 外文会议>Conference on Embedded Processors for Multimedia and Communications; 20040119-20040120; San Jose,CA; US >A Low-power VLSI Implementation for Variable Length Decoder in MPEG-1 Layer Ⅲ
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A Low-power VLSI Implementation for Variable Length Decoder in MPEG-1 Layer Ⅲ

机译:MPEG-1第三层中可变长度解码器的低功耗VLSI实现

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MPEG Layer Ⅲ (MP3) audio coding algorithm is a widely used audio coding standard. It involves several complex coding techniques and is therefore difficult to create an efficient architecture design. The variable length decoding (VLD) e.g. Huffman decoding, is an important part of MP3, which needs great amount of search and memory access operations. In this paper a data driven variable length decoding algorithm is presented, which exploits the signal statistics of variable length codes to reduce power and a two-level table lookup method is presented. The decoder was designed based on simplicity and low-cost, low power consumption while retaining the high efficiency requirements. The total power saving is about 67%.
机译:MPEG LayerⅢ(MP3)音频编码算法是一种广泛使用的音频编码标准。它涉及几种复杂的编码技术,因此很难创建有效的体系结构设计。可变长度解码(VLD)霍夫曼解码是MP3的重要组成部分,需要大量的搜索和内存访问操作。本文提出了一种数据驱动的可变长度解码算法,该算法利用可变长度代码的信号统计量来降低功耗,并提出了一种两级表查找方法。该解码器的设计基于简单性,低成本,低功耗,同时又保留了高效率要求。总节能量约为67%。

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