Implementation of a MPEG 1 layer I audio decoder with variable bit lengths

摘要

One of the most popular forms of audio compression is MPEG (Moving Picture Experts Group). By using a VHDL (Very high-speed integrated circuit Hardware Description Language) implementation of a MPEG audio decoder and varying the word length of the constants and the multiplications used in the decoding process, and comparing the error, the minimum word length required can be determined. In general, the smaller the word length, the smaller the hardware resources required. This thesis is an investigation to find the minimum bit lengths required for each of the four multiplication sections used in a MPEG Audio decoder, that will still meet the quality levels specified in the MPEG standard. The use of the minimum bit lengths allows the minimum area resources of a FPGA (Field Programmable Gate Array) to be used. A FPGA model was designed that allowed the number of bits used to represent four constants and the results of the multiplications using these constants to vary. In order to limit the amount of data generated, testing was restricted to a single channel of audio data sampled at a frequency of 32kHz. This was then compared to the supplied C model distributed with the MPEG Audio Standard. It was found that for the MPEG audio coder to be fully compliant with the standard the bit lengths of the constants and the multiplications could be reduced by 75% and to be partial compliant with the standard, the bit lengths of the constants and the multiplications could be reduced by up to 82%. An implementation of a MPEG audio decoder in VHDL has the advantage of specific hardware, optimised, for all the different complex mathematical operations thereby reducing the repetitive operations and therefore power consumption and the time required performing these complex operations.