Investigations and Physical Modelling of Saturation Effects in Lateral DMOS Transistor Architectures Based on the Concept of Intrinsic Drain Voltage

摘要

Thorough investigations of the saturation phenomena in state-of-the-art HV Lateral DMOS architectures (L-DMOS and X-DMOS), based on 2D numerical simulation and on the new concept of intrinsic drain potential, V_K, are presented. The paper highlights the V_K solution in all operation regimes, analyses the corresponding complex quasi-saturation mechanisms and originally demonstrates that this key potential remains at a low-voltage and shows a marked maximum value at low V_G. A simple and accurate analytical modelling strategy, which is usable for any architecture-specific bias-dependence of the drift region equivalent resistance is proposed based on the V_K-concept. Very good model performances using a BSIM3v3 low-voltage model combined with the proposed intrinsic MOSFET strategy are reported.