Generating Mask Inspection Rules for Advanced Lithography

摘要

Semiconductor product designs are necessarily constrained by both the wafer and mask lithographic capabilities. When mask image sizes approach the exposure wavelength, optical and resist effects distort the printed images. Applying optical proximity correction (OPC) to design features on the mask compensates for diffraction effects. However, aggressive OPC introduces even smaller minimum features, adds notches and bulges, introduces sub-resolution assist features (SRAFs) and generally creates a more challenging mask design with respect to data handling, printing and inspection. Mask defect inspection is a critical part of the mask process, ensuring that the mask pattern matches the intended design. However, the inspection itself imposes constraints on mask patterns that can be inspected with high defect sensitivity but low nuisance defect counts. These additional restrictions are undesirable since they can reduce the effectiveness of the OPC. IBM and KLA-Tencor have developed a test mask methodology to investigate the inspectability limits of the 576 and 516 mask inspection systems. The test mask design contains a variety of rules or features that currently impose inspectability limits on the inspection tools, in a range of sizes. The design also incorporates many features essential for obtaining valid results, such as a user-friendly layout, multiple pattern orientations, and background patterns. The mask was built and inspected in IBM Burlington's mask house. Preliminary inspection results will be presented; they underscore the importance of understanding both the inspection tool and the mask process when restricting mask design rules.